1. Field of the Invention
The present invention relates to design of a large-scale integration (LSI), such as a structured application specific integrated circuit (ASIC).
2. Description of the Related Art
Conventionally, ASICs, field programmable gate arrays (FPGA) and structured ASICs are available as application specific LSI circuits. The ASIC has transistor and metal layers specific to the type of LSI to be manufactured that formed on the surface of a silicon wafer (e.g., Japanese Patent Application Laid-Open Publication No. H06-29391).
The FPGA is designed to have its logic components (circuit function) configured after manufacturing, thereby enabling a user to change the behavior by programming after the manufacturing of the LSI.
The structured ASIC has a common transistor layer (or a transistor layer and a metal 1 layer) formed on the surface of a silicon wafer, and by changing the wiring pattern of the metal layer formed thereon, operation of the LSI is determined.
However, for the above-mentioned conventional technologies, as speed variations in LSI operation result depending on conditions at the time of manufacturing, it is difficult to control the performance of LSI to be manufactured. Furthermore, since ASIC and structured ASIC are application specific, design must ensure that after manufacturing, all units meet specified performance levels.
For ASIC and structured ASIC, a great deal of time and cost may be required for the timing design to ensure the performance required for the specific application. In such a case, a design period may be shortened conceivably by using only units that meet performance specifications
Since ASIC and structured ASIC, are manufactured specific to an application, units that do not meet performance requirements for the specific application can not be utilized for other applications and hence become useless, resulting in a problem of increased manufacturing cost.
Also, variations in current leakage result depending on the conditions at the time of manufacturing. For this reason, in selection of a package for encapsulating chips, to accommodate chips with high current leakage, a package having a high unit cost is selected.
However, for a chip with a small current leakage, this selection process results in the use of an unnecessarily expensive package, further resulting in a problem of an increased manufacturing cost. Furthermore, in LSIs for which there are great restrictions in terms of power consumption and chip unit price for manufacturing, a great deal of time may be spent on the design to satisfy such restrictions, and thereby leading to a problem of a longer design period.
In the case of FPGA, since logic components are configured after the manufacturing of the LSI, a design change can be made relatively easily at the time of occurrence of a failure. However, a problem with FPGA is that in addition to a high chip unit price, the performance of the LSI that can be manufactured is inferior to that of the ASIC or the structured ASIC.